1. Technical Field
The present invention relates generally to the execution of instructions belonging to a set of instructions having a same format, and relates in particular to a hardware device for parallel processing of any instructions within a set of instructions.
2. Prior Art
The execution of any instruction within a set of instructions having the same format in a computer, processor or any other data processing unit, can be graphically represented by an algorithm including a plurality of processes and decisions. Such decisions of a binary type enable, according to the operand fields of the instruction, to know which are the processes to be run for the execution of the instruction. In other words, each instruction corresponds to a specific combination of processes which is different from the other instructions due to the choice between two paths made at each decision which is met.
For example, a simple algorithm illustrated in FIG. 1 includes three processes P1, P2, P3 and two decisions D1, D2, and corresponds to the graphical representation of three instructions. The first instruction is represented by the algorithm flow when decision D1 is yes, that is when processes P1 and P2 are to be executed. The second instruction is represented by the algorithm flow when decision D1 is no and decision D2 is yes, that is when processes P1 and P3 are to be executed. Finally, the third instruction is represented by the algorithm flow when decision D1 is no and decision D2 is also no, that is when only process P1 is to be executed. Note that looping back to the entry point of the algorithm after decision D2 comes down to execute a new instruction within the set of instructions.
Each process may be independent or can depend on another process. Thus, in the first instruction which consists in executing processes P1 and P2 process P2 may depend upon the result of process P1 but may also be independent. Likewise for the second instruction where process P3 may depend on the result of process P1 or may be independent.
Today, the execution of an instruction represented by the algorithm illustrated in FIG. 1 is made on a sequential basis. This means that decision D1 is taken after process P1 has been executed, process P2 is executed after decision D1 has been determined as being yes, and process P3 can be executed only after decision D2 has been determined as being yes. Therefore, the state of the art does not enable an important speed in the run of the algorithm, principally when each instruction is dependant upon taking a lot of decisions during its execution.
The main object of the invention is to provide a programmable hardware enabling any instruction of a set of instructions to be executed in a parallel and exclusive way thereby resulting in a high execution speed.
The invention relates therefore to a hardware device for parallel processing a determined instruction of a set of instructions having a same format defining operand fields and other data fields, the execution of this determined instruction being represented as an algorithm comprising a plurality of processes, the processing of which depends on decisions. This device comprises means for activating the processing of one or several processes determined by the operand fields of the instruction, decision macroblock being each associated with a specific instruction of the set of instructions, only one decision macroblock being selected by the determined instruction in order to determine which are the process(es) to be activated for executing the determined instruction.
According to a preferred embodiment of the invention, each decision macroblock comprises a mask register having the same length as the determined instruction and containing a mask for masking the bits of the other data fields, and a value register containing a value having the same length as the determined instruction and composed of a defined part corresponding and being identical to the operand fields of the specific instruction, and combinatory logic means for logically combining the determined instruction with the contents of the mask register and the contents of the value register so that the output of the macroblock is 1 only when the determined instruction is the specific instruction associated with the macroblock.